The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit suitable for realizing an increased high degree of integration thereof and also for reducing areas of devices and interconnections thereof.
The semiconductor integrated circuit has p-channel and n-channel MOS field effect transistors acting as switching devices. In order to control the switching operations of the MOS field effect transistor, it is required to apply the gate control signal to the gate electrode of the MOS field effect transistors. A ground level gate control signal is applied to the gate electrode of the p-channel MOS field effect transistor. A power voltage level gate control signal is applied to the gate electrode of the n-channel MOS field effect transistor. It is also necessary to render the gate electrode have a surge resistance against electrostatic or to prevent the device from being broken due to electrostatic discharge, for which purposes the gate signal is required to be applied to the gate electrode through a certain resistance of, for example, a few k.OMEGA..
Such the above n-channel and p-channel MOS field effect transistors having the resistances against the gate electrostatic discharge have normally been designed in accordance with the normal layout standard, wherein a distance between adjacent two of source pads is set at a predetermined value.
Further, other n-channel and p-channel MOS field effect transistors having the resistances against the source electrostatic discharge have been known, wherein a ground level signal is applied to the source electrode of the p-channel MOS field effect transistor or a power voltage level is applied to the source electrode of the n-channel MOS field effect transistor. The design standards are specific layout standard or electrostatic discharge standard, wherein a distance of the adjacent two of the source pads is larger than in the above normal layout standard.
FIG. 1 is a circuit diagram illustrative of a first conventional semiconductor integrated circuit. The first conventional semiconductor integrated circuit comprises first and second p-channel MOS field effect transistors P1 and P2 and four n-channel MOS field effect transistors N1, N2, N3 and N4 as well as a first invertor INV. A first series connection of the first p-channel MOS field effect transistor P1, the first n-channel MOS field effect transistor N1 and the third n-channel MOS field effect transistor N3 is formed between a high voltage line and a ground line. A second series connection of the second p-channel MOS field effect transistor P2, the second n-channel MOS field effect transistor N2 and the fourth n-channel MOS field effect transistor N4 is also formed between the high voltage line and the ground line.
The first p-channel MOS field effect transistor P1 is connected in series between the high voltage line and the first n-channel MOS field effect transistor N1. A gate of the first p-channel MOS field effect transistor P1 is also connected to a second node 2 between the second p-channel MOS field effect transistor P2 and the second n-channel MOS field effect transistor N2. The first n-channel MOS field effect transistor N1 is connected in series between the first p-channel MOS field effect transistor P1 and the third n-channel MOS field effect transistor N3. A gate of the first n-channel MOS field effect transistor N1 is applied with a high power voltage VCC The third n-channel MOS field effect transistor N3 is connected in series between the first n-channel MOS field effect transistor N1 and the ground line. A gate of the third n-channel MOS field effect transistor N3 receives a gate control signal of high level "H" or low level "L". The gate of the third n-channel MOS field effect transistor N3 is also connected to an input side of the first invertor INV.
The second p-channel MOS field effect transistor P2 is connected in series between the high voltage line and the second n-channel MOS field effect transistor N2. A gate of the second p-channel MOS field effect transistor P2 is also connected to a first node 1 between the first p-channel MOS field effect transistor P1 and the first n-channel MOS field effect transistor N1 The second n-channel MOS field effect transistor N2 is connected in series between the second p-channel MOS field effect transistor P2 and the fourth n-channel MOS field effect transistor N4. A gate of the second n-channel MOS field effect transistor N2 is connected to the gate of the first n-channel MOS field effect transistor N1 and thus is applied with the high power voltage VCC. The fourth n-channel MOS field effect transistor N4 is connected in series between the second n-channel MOS field effect transistor N2 and the ground line. A gate of the fourth n-channel MOS field effect transistor N4 is connected to an output side of the first invertor INV for receiving an output signal from the first invertor into which the gate control signal of high level "H" or low level "L" is inputted, so that the gate of the fourth n-channel MOS field effect transistor N4 receives the inverted signal to the gate control signal which is applied to the gate of the third n-channel MOS field effect transistor N3.
The above circuit acts as a level shifter. The gate levels of the first and second n-channel MOS field effect transistors N1 and N2 are fixed at the high power voltage level VCC, so as to reduce the voltage level to be applied to the third and fourth n-channel MOS field effect transistors N3 and N4 by a threshold voltage of the n-channel MOS field effect transistor for relaxation of the stress.
The gate electrostatic discharge resistant type p-channel and n-channel MOS field effect transistors are applicable for various purposes such as for obtaining a pull-up voltage from the high power voltage VCC or obtaining a pull-down voltage from the ground level.
A method of laying out resistances on semiconductor integrated circuits having gate electrostatic discharge resistant type MOS field effect transistors will subsequently be described.
FIG. 2 is a diagram illustrative of a conventional layout of the resistances in a part of the semiconductor integrated circuit in FIG. 1. A first MOS field effect transistor 2a and a second MOS field effect transistor 3 are shown in FIG. 2. The first MOS field effect transistor 2a shown in FIG. 2 may correspond to the first p-channel MOS field effect transistor P1 shown in FIG. 1. The second MOS field effect transistor 3 shown in FIG. 2 may correspond to the first n-channel MOS field effect transistor N1 shown in FIG. 1. The gate of the second MOS field effect transistor 3 corresponding to the first n-channel MOS field effect transistor N1 is also connected through an interconnection 4a to the source of the first MOS field effect transistor 2a corresponding to the first p-channel MOS field effect transistor P1. A resistance 5 of a few k-ohms is also formed between the source contacts "S" of the first MOS field effect transistor 2a, so that the resistance 5 is connected between the high power voltage line and the source electrode of the first MOS field effect transistor 2a. The resistance 5 may be formed by partially removing the source contacts and utilizing diffusion layers of the first MOS field effect transistor 2a.
When the resistive diffusion regions are individually provided, the resistance region of a few k-ohms are required to be designed in the electrostatic discharge standard, so that each of the resistive diffusion regions is larger in occupied area than what is designed in the normal standard whereby the total area of the semiconductor integrated circuit is also increased.
Alternative method of forming the resistance having already been known in the art will be described FIG. 3 is a diagram illustrative of another conventional layout of the resistances in a part of the semiconductor integrated circuit in FIG. 1. A power supply resistive region 1a' is separately provided which acts as a resistance only but not performs as transistor, so that a resistance 5 of a few k-ohms is formed in the power supply resistive region 1a'. The power supply resistive region 1a' has a guard ring 6 in circumferential portions of the power supply resistive region 1a' for preventing latch-up phenomenon. The peripheral portions of the electrostatic discharge standard region and the n-channel and p-channel MOS field effect transistors are also surrounded by the guard rings. A resistive diffusion region 5 is formed in the resistive region 1a and surrounded by the guard ring 6, wherein the resistive diffusion region 5 extends from the power contact 11 to another contact 12. The other contact 12 is to be connected to the gate of the transistor The resistive diffusion region 5 acts as a resistance between the power contact 11 and the other contact 12. The resistive diffusion region 5 is partially expanded but only around the power contact 11, so that the resistive diffusion region 5 increases in width around the power contact 11 to surround the power contact, whilst the remaining part of the resistive diffusion region 5 has a standard width which is much narrower than the expanded portion thereof around the power contact 11. Consequently, it is necessary that the resistive diffusion region 5 is designed in the electrostatic discharge standard wherein the distance is more wide than the normal standard for allowing the formation of the expanding portion of the resistive diffusion region 5.
When the resistive diffusion regions are individually provided, the resistance region of a few k-ohms are required to be designed in the electrostatic discharge standard, so that each of the resistive diffusion regions is larger in occupied area than what is designed in the normal standard, whereby the total area of the semiconductor integrated circuit is also increased.
FIG. 4 is a diagram illustrative of the conventional layout of the semiconductor integrated circuit using the transistor region of FIG. 2 or the resistance region of FIG 3. A single power source transistor region 1a is formed commonly to a plurality of the transistors 3, for example, four transistors 3, wherein the gate contact of each of the four transistors 3 is connected through the interconnection 4a to the single power source transistor region la, so that the four transistors 3 are connected to the single power source transistor region 1a in parallel to each other. In such layout, the increase in the number of the transistors 3 connected to the single power source transistor region 1a in parallel to each other results in the increase in the length of the interconnection 4a which connects the transistors 3 to the single power source transistor region 1a.
When the single resistive diffusion region is provided commonly to a plurality of the transistors, the interconnections are provided for connecting the individual transistors to the single and common resistive diffusion region, whereby the individual interconnections are increased in length and thus the total occupied area of the plural interconnections is also increased. As a result, the total area of the semiconductor integrated circuit is also increased.
The following descriptions will focus on the conventional layout of the source electrostatic discharge resistant n-channel and p-channel MOS field effect transistors. The power voltage level is applied to the source of the source electrostatic discharge resistant type n-channel MOS field effect transistor. The ground level is also applied to the source of the source electrostatic discharge resistant p-channel MOS field effect transistor.
FIG. 5A is a diagram illustrative of the conventional source electrostatic discharge resistant type n-channel MOS field effect transistor. FIG. 5B is a diagram illustrative of the conventional layout of a plurality of the conventional source electrostatic discharge resistant type n-channel MOS field effect transistor shown in FIG. 5A. As illustrated in FIG. 5A, the conventional source electrostatic discharge resistant type n-channel MOS field effect transistor 7 is designed in a larger electrostatic discharge standard than the normal layout standard. Namely, the design is so made as to keep sufficient distances "t1", "t2" and "t3" of the source contact "S" from four edges of the source diffusion region in order to increase the resistance for stress relaxation, thereby suppressing concentration of charges at the source contact "S" for preventing p-n junction from being broken. Drain contacts "D" are formed in a drain diffusion region separated from the source diffusion region by a channel region over which a gate electrode "G" is formed. Namely, the distances "t1" and "t2" between the source contact "S" and the edges of the source diffusion region and also the distance "t3" between the source contact "S" and the gate electrode "G" are wider than what is designed in the normal standard.
When the semiconductor integrated circuit is designed with use of such the conventional source electrostatic discharge resistant type MOS field effect transistor as shown in FIG. 5A, then it is necessary to apply the above electrostatic standard to all of the transistors, whereby a total area of the semiconductor integrated circuit is remarkably increased. Namely, as illustrated in FIG. 5B, each of the conventional source electrostatic discharge resistant type MOS field effect transistors 7 is deigned in the above electrostatic standard so that the each of the conventional source electrostatic discharge resistant type MOS field effect transistors 7 is larger in occupied area than the normal layout standard, for which reason the total occupied area of the semiconductor integrated circuit is made much larger than that designed in the normal standard.
In the above circumstances, it had been required to develop a novel semiconductor integrated circuit suitable for realizing an increased high degree of integration thereof and also for reducing areas of devices and interconnections thereof.